This results in dramatic processor performance improvements. The ISEF can execute entire sections of application code in a single instruction. The tightly coupled nature of the hardware ensures that the intelligent compiler can optimize instruction issues and maximize performance. With automatic characterization of the hardware "instruction," the Instruction Set Simulator in the Stretch tool suite is able to simulate the algorithm flow with cycle accurate prediction.
The ISEF can be supplied with data from a set of 128-bit wide registers. The ISEF contains embedded ISEF RAM (IRAM) that can be used to store the data, intermediate results, lookup tables, or tables of operands. IRAM is mapped into the processor's memory space and can be accessed directly. Data can also be moved in and out of the IRAM, without consuming any processor bandwidth, with a dedicated DMA engine.