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Second Generation ISEF
The Second Generation Instruction Set Extension Fabric (ISEF) is the programmable fabric that sits within the data path of a Tensilica Xtensa LX processor. System designers can implement portions of a required algorithm in hardware by using the Stretch ISEF. In this way, the instruction issue logic of the processor, as well as the intelligent compiler, can make full use of these hardware functions and schedule them into the instruction execution flow.

The result is a dramatic improvement in processor performance. The ISEF can now execute entire sections of application code in a single instruction. The tightly coupled nature of the hardware ensures that the intelligent compiler is able to optimize instruction issues to maximize performance. With automatic characterization of the hardware "instruction," the Instruction Set Simulator in the Stretch tool suite is able to simulate the algorithm flow with cycle accurate prediction.

S6SCP Engine

The Second Generation ISEF can be supplied with data from a set of 128-bit wide registers in the same way as previous generations of Stretch processors. For the S6000 family, 64KB of embedded RAM has been added to the ISEF. This embedded ISEF RAM (IRAM) can be used to store data, intermediate results, lookup tables, or tables of operands. IRAM is mapped into the processor's memory space and can be accessed directly. Data can also be moved in and out of the IRAM, without consuming any processor bandwidth, with a dedicated DMA engine.